By Topic

Mapping the MD5 hash algorithm onto the NAPA architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

National Semiconductor's Adaptive Processing Architecture (NAPA) integrates a Fixed Instruction set Processor (FIP), an Adaptive Logic Processor (ALP), memory and other support circuitry into a single reconfigurable computing device. In the NAPA1000 the FIP is a small 32-bit RISC microprocessor and the ALP is a 64×96 array of fine grain reconfigurable logic cells. The NAPA1000 also contains two banks of 2048×32 Pipeline Memory Array (PMA), eight banks of 256×8 Scratchpad Memory Array (SMA), and one bank of 1024×32 Local Memory Array (LMA). External to the NAPA1000 are two banks of DRAM and an interface to a host computer. The Toggle Bus transceiver is the interface to a multi-stage interconnect network, and is capable of performing arbitrary reflections and rotations on 32-bit words. The Reconfiguration Pipeline Control unit (RPC) can also serve as a DMA engine

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998