Referenced Items are not available for this document.
This paper describes a VLSI implementation of a multistage self-routing ATM switch fabric. The size of the switch prototype is 16×16 and is designed to handle the OC-12 (622 Mbps) link rate. Based on a bit-slice architecture, the entire 16×16 switch is implemented using four identical chips. The switch has multiple paths, created by a randomizer in front of the routing stages, between each input-output pair. The switch uses an input/output-buffering scheme and contains no buffers inside the fabric. To facilitate fault detection and isolation, we add automatic fault detection schemes at the node, chip, and system levels of the design
Published in:
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
(Volume:6
)
Date of Conference: 31 May-3 Jun 1998
- Page(s):
- 478 - 481 vol.6
- Meeting Date :
- 31 May 1998-03 Jun 1998
- Print ISBN:
- 0-7803-4455-3
- INSPEC Accession Number:
- 6054213
- Conference Location :
- Monterey, CA
- Digital Object Identifier :
- 10.1109/ISCAS.1998.705315
- Product Type:
- Conference Publications
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