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A system LSI utilizing media processor core “MMA”

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6 Author(s)
Kamijo, S. ; Fujitsu Labs. Ltd., Kawasaki, Japan ; Wakimoto, Y. ; Satoh, T. ; Sakurai, A.
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We have developed a system LSI utilizing media processor core “MMA”. The LSI will be ready to deliver to general customers from Jan. 1998. The MMA is a processor core which offers 1BOPS of performance at 180 MHz to realize MPEG2 real time decoding. The MMA size is 3.3 mm*3.1 mm in the implementation utilizing 3 ML 0.35 um technology. This is handy enough to integrate with various function blocks, such as GDC, bus bridges to form a system LSI dedicated for real time multi-media operations. The LSI runs at 100 MHz accompanying SPARClite RISC CPU. For the concurrent operations between the LSI and SPARClite, a dedicated task queuing scheme has been defined to maximize the sustained performance. In this paper, we describe the architecture of the LSI, and discuss our performance evaluation result of MPEG decoding utilizing this task queuing scheme

Published in:

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Date of Conference:

11-14 May 1998