By Topic

A technique for automated validation of fault tolerant designs using laser fault injection (LFI)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Samson, J.R., Jr. ; Honeywell Inc., Clearwater, FL, USA ; Moreno, W. ; Falquez, F.

This paper describes the successful development and demonstration of a Laser Fault Injection (LFI) technique to inject soft, i.e., transient, faults into VLSI circuits in a precisely-controlled, non-destructive, non-intrusive manner for the purpose of validating fault tolerant design and performance. The technique described in this paper not only enables the validation of fault-tolerant VLSI designs, but it also offers the potential for performing automated testing of board-level and system-level fault tolerant designs including fault tolerant operating system and application software. The paper describes the results of LFI testing performed to date on test metal circuit structures, i.e., ring oscillators, flip-flops, and multiplier chains, and on an advanced RISC processor, with comprehensive on-chip concurrent error detection and instruction retry, in a working single board computer. Relative to rapid, low cost testing and validation of complex fault tolerant designs, with the automated laser system at the Laser Restructuring Facility at the University of South Florida Center for Microelectronics Research (USF/CMR), a design with 10000 test points could be tested and validated in under 17 minutes. In addition to describing the successful demonstration of the technique to date, the paper discusses some of the challenges that still need to be addressed to make the technique a truly practical fault tolerant design validation tool.

Published in:

Fault-Tolerant Computing, 1998. Digest of Papers. Twenty-Eighth Annual International Symposium on

Date of Conference:

23-25 June 1998