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A self-reference read scheme for a 1T/1C FeRAM

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4 Author(s)
J. Yamada ; Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan ; T. Miwa ; H. Koike ; H. Toyoshima

This paper describes a self-reference read scheme for use with 1T/1C FeRAMs. It is able to overcome the reference voltage problem faced by conventional 1T/1C FeRAMs without the use of any reference cells. The proposed scheme employs a memory cell that is accessed twice, and it uses this cell to generate a reference voltage. This self-generated reference voltage is automatically kept between read bit line voltages, which correspond to stored data ("1" and "0"). We have designed and fabricated a test device, and confirmed the viability of the read scheme.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998