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A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories

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5 Author(s)
Takeuchi, K. ; Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; Satoh, S. ; Tanaka, T. ; Imamiya, K.
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This paper proposes a new NAND flash memory and related novel circuit techniques that suppress the program disturb and realize a smaller cell size with minimum array noise. The memory cell realizes a LOCOS width reduction of 20%. This architecture is essential for a scaled STI cell because of the improved program disturb. The proposed column latch and Vcc-bitline shield sensing method enable excellent noise immunity and decrease the Vth distribution from 1.2 V to 0.6 V. They also improve device reliability.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998