A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories

This paper proposes a new NAND flash memory and related novel circuit techniques that suppress the program disturb and realize a smaller cell size with minimum array noise. The memory cell realizes a LOCOS width reduction of 20%. This architecture is essential for a scaled STI cell because of the improved program disturb. The proposed column latch and Vcc-bitline shield sensing method enable excellent noise immunity and decrease the Vth distribution from 1.2 V to 0.6 V. They also improve device reliability.