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A 2 Gb/s/pin CMOS asymmetric serial link

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5 Author(s)
Kun-Yung Ken Chang ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Ellersick, W. ; Shang-Tse Chuang ; Sidiropoulos, S.
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The design of an asymmetric serial link poses a number of tradeoffs for the designer. This paper describes measurements from a 0.25 /spl mu/m CMOS test chip which show that a properly designed asymmetric link can achieve 2 Gb/s using single-ended signalling with a bit-error rate <10/sup -14/.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998