A jitter and data duty distortion tolerated PLL circuit for 156-Mbps burst-mode transmission

A new PLL circuit for 156-Mbps burst-mode transmission application in a passive optical network (PON) is described in this paper. For data recognition accuracy and jitter tolerance, we propose an ADR (adaptive data recognition) circuit using rising and falling phase average values extracted from input burst-mode data, and an EPA (edge phase averaging) circuit averaging rising and falling edge phases of input burst-mode data. The PLL circuit has been implemented on 3.3 V, 0.35 /spl mu/m CMOS standard cell, and has shown good system performance, such as a power penalty of less than 0.1 dB at 10/sup -8/ error rate.