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A 1.5 V, 10-bit, 14.3 MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak SNDR of 58.5 dB, maximum DNL of 0.51 LSB, maximum INL of 0.66 LSB and a power consumption of 36 mW.
Date of Conference: 11-13 June 1998