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A CMOS 260 Mbps read channel with EPRML performance

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7 Author(s)
Conway, T. ; Analog Devices BV, Limerick, Ireland ; Quinlan, P. ; Spalding, J. ; Hitchcox, D.
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In this paper, the read channel architecture for a 260 Mbps read channel far magnetic recording applications is presented. The read channel uses a 7 pole 2 zero continuous time filter with a 6 bit flash ADC in the analog front end. The ADC samples are further equalized to the PR4 partial response target with a 5 tap fully asymmetric FIR including LMS adaption. Detection is performed with a PR4 Viterbi detector followed by a postprocessor based on a 16/17(0,6/6) modulation code achieving full EPR4 performance over a range of channel densities. The design is implemented in 0.35 /spl mu/m DPTM CMOS and dissipates 1.3 W max at 260 Mbps.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998

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