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A 480 MHz 11 mW PR4 Viterbi detector and margin circuit in 0.25 /spl mu/m CMOS

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1 Author(s)
Thon, L.E. ; IBM Almaden Res. Center, San Jose, CA, USA

This paper describes a Viterbi detector and margin circuit for PR4 magnetic recording channels. The implementation uses a modified difference-metric formulation of the Viterbi algorithm (VA). A Viterbi margin (VM) function is included for channel quality checking purposes. Modifications and implementation techniques that optimize power consumption and speed are described. The VA+VM circuit includes 24+24 bits of path and margin memory, uses 11 mW of power (7 mW for VA alone) at 480 MHz and occupies 0.052 mm/sup 2/ in a 0.25 /spl mu/m 1.8 V CMOS process.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998