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This paper describes a logic circuit family which is used extensively in 1.0 GHz single-issue 64-bit PowerPC integer processor. The family consists of an incrementor, a count-leading-zero, a rotator, and a ROM. Each macro consists of a leaf-cell array, dual rail bit-lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read out scheme of sensing the differential voltage of dual rail bit-lines is used. The hardware is fabricated in a 0.25 /spl mu/m mask channel length, 6-metal-layer (Al) CMOS technology (1.8 V nom. V/sub DD/).
Date of Conference: 11-13 June 1998