An on-chip timing adjuster with sub-100-ps resolution for a high-speed DRAM interface

A novel fully digital fine-delay generator for a high-speed DRAM interface is proposed. The generator consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-/spl mu/m technology demonstrates that a resolution of 26 ps can be realized. A timing adjuster using the generator has 2-clock-cycle lock-in time and sub-100-ps error.