Referenced Items are not available for this document.
We proposed a compact delay line scheme, ring delay line (RDL). It has a ring topology instead of linear one. The ring time-to-digital converter (TDC) works with wide range of operating frequencies with the help of a shift register. Since the silicon area of ring TDC is negligible, RDL consumes about half of the other linear delay line's area. Its locking time is found to be 2 clock cycles and operating current is less than 1 mA.
Published in:
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Date of Conference: 11-13 June 1998
- Page(s):
- 60 - 61
- Meeting Date :
- 11 Jun 1998-13 Jun 1998
- Print ISBN:
- 0-7803-4766-8
- INSPEC Accession Number:
- 6096009
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1998.688003
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
