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A 2 V 900 MHz CMOS phase-locked loop

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3 Author(s)
Jieh-Tsorng Wu ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Mu-Jung Chen ; Cheng-Chung Hsu

A 2 V 60 mW 900 MHz CMOS phase-locked loop is fabricated using a 0.6 /spl mu/m CMOS technology. The negative-G/sub m/ LC-tuned oscillator employs a variable impedance converter for frequency tuning, and shows a frequency range from 808 MHz to 920 MHz. When phase-locked to an 112.5 MHz reference, the measured phase noise of the 900 MHz output is -96.5 dBc/Hz at 100 kHz offset. Chip size is 2270/spl times/2600 /spl mu/m/sup 2/.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998