Comparison of AND-XOR logic synthesis using a genetic algorithm against MISII for implementation on FPGAs

A method for synthesising and implementing PLA-type logic functions in multilevel AND-XOR form is presented. This uses a combination of developed minimisation rules, and a genetic algorithm to select input variable ordering. The purpose of this is to create an AND-XOR synthesis tool which allows designers a flexible method of implementing logic systems compactly on field-programmable gate arrays (FPGA). Results show that some benchmark functions require fewer CLBs on the FPGA parts than conventional Boolean minimisation using MISII.