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Efficient partitioning method for distributed logic simulation of VLSI circuits

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2 Author(s)
Guettaf, A. ; Univ. Pierre et Marie Curie, Paris, France ; Bazargan-Sabet, P.

Distributed simulation is expected to provide a significant speed up of simulation run time. Partitioning and load balancing are very influential factors for speed up. The paper presents an efficient partitioning method for distributed VLSI circuits simulation. The main features of this method are the use of a logic replication algorithm. A realistic cost function based on precalculated activity of the circuit using a probabilistic algorithm, and a the balance between execution cost and communication cost. A distributed simulator based on a conservative synchronization method has been used to evaluate the performance of the partitioning

Published in:

Simulation Symposium, 1998. Proceedings. 31st Annual

Date of Conference:

5-9 Apr 1998