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A FIFO data switch design experiment

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5 Author(s)
Coates, W.S. ; Sun Microsyst. Labs., Palo Alto, CA, USA ; Lexau, J.K. ; Jones, I.W. ; Fairbanks, S.M.
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A core problem in many pipelined circuit designs is data-dependent data flow. We describe a methodology and a set of circuit modules to address this problem in the asynchronous domain. We call our methodology P**3, or “P cubed”. Items flowing through a set of FIFO datapaths can be conditionally steered under the control of data carried by other FIFOs. We have used the P**3 methodology to design and implement a FIFO rest chip that uses a data-dependent switch to delete marked data items conditionally. The circuit uses two on-chip FIFO rings as high-speed data sources. It was fabricated through MOSIS using their 0.6 μ CMOS design rules. The peak data switch throughput was measured to be a minimum of 580 million data items per second at nominal Vdd of 3.3 V

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on

Date of Conference:

30 Mar-2 Apr 1998

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