By Topic

Analysis of adaptive CMOS down conversion mixers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
C. K. Sandalci ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; S. Kiaei

Analysis of CMOS direct conversion architecture with adaptive DC offset compensation is presented. Due to process mismatches and local oscillator (LO) crosstalk, DC offsets up to 30 mV are observed at the mixer output. For a practical direct conversion or zero-IF down-conversion system, the incoming RF signal can be as low as -100 dBm or few microvolts at this stage and any LO coupling will cause a DC offset orders of magnitude larger than the received signal. The DC offset needs to be effectively reduced to prevent the consecutive gain stages from entering saturation and destroying the RF signal. To achieve this, an adaptive DC shifting circuit is presented. Adding a tunable DC offset on the LO signal can effectively counteract the output DC offset by exploiting the quadratic LO dependence of the process mismatch induced offsets. In addition to that, DSP approaches for adaptively generating the control signals for the DC shifting circuitry are investigated

Published in:

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Date of Conference:

19-21 Feb 1998