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The quantization error characteristics of the signed-digit arithmetic are studied for the application to the MSD (Most Significant Digit) first digit serial computation, where only truncation is allowed for the word-length reduction of the multiplied results. This study shows that truncated results in the signed-digit arithmetic contain very little DC error when a symmetric remainder reduction scheme is employed. The error characteristics are similar to those of the rounding scheme in the two's complement number system. However, the symmetric remainder reduction scheme demands more hardware and delay than the asymmetric reduction scheme.