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This paper presents an architecture for 2-D image decomposition of discrete wavelet transform. In order to avoid the memory transpose problem, we use non-separable approach instead of separable one. Besides, based on the input data reuse concept, a parallel-pipelined architecture is proposed The main characteristics of this architecture include: (1) needless memory transposition; (2) lower hardware cost; (3) shorter latency; (4) suitable VLSI implementation. Finally, all components in our architecture are simulated based on the accuracy requirement and realized as a single chip physically.