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A CMOS robust fully-balanced-signal generator

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4 Author(s)
Changku Hwang ; Micrys Inc., Colombus, OH, USA ; Hyogo, A. ; Ismail, M. ; Moon, G.

In this paper a new single-ended-input fully-balanced-output circuit (SFC) is proposed as an input interface for fully balanced signal processing systems. The new SFC can overcome the drawback of uncontrollable process variation of resistors and generate well-controlled process invariant common mode output voltage, V0, com. The adopted active current common mode feedback compensation makes this possible. Simulations have been carried out using MOSIS 2 μm N-well process and a 3 V supply, showing that with ±100% variation of resistor V0, com only varies by less than ±2%. In addition, it is shown that V0, com is accurately controlled by a preset DC voltage.

Published in:

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on  (Volume:2 )

Date of Conference:

3-6 Aug. 1997