A 'do-it-yourself' methodology for CMOS transistor mismatch characterization

This paper presents a 'do-it-yourself' methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, sweeping transistors width W and length L. The standard deviation of the mismatch of these parameters is computed (/sup /spl sigma//(/spl Delta//spl beta///spl beta/), /sup /spl sigma//(/spl Delta/v/sub /spl gamma/0/), /sup /spl sigma//(/spl Delta//spl gamma/)) for each transistor type and size, as well as the statistical correlation factors between them. These standard deviations and correlations are fitted to two dimensional surfaces /spl sigma/(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in good agreement.