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A review of 3-D packaging technology

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3 Author(s)
S. F. Al-Sarawi ; Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia ; D. Abbott ; P. D. Franzon

This paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in detail. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, and are briefly discussed

Published in:

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B  (Volume:21 ,  Issue: 1 )