Building fast bundled data circuits with a specialized standard cell library

A method for building fast, optimized bundled data circuits from a specialized CMOS standard cell library is presented. The method has been successfully used for the design of a FIFO buffer for a multicomputer network. This chip, which contains about 19000 transistors in a 1.5 /spl mu/m CMOS process, achieves a throughput of about 150 million symbols per second.