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Building fast bundled data circuits with a specialized standard cell library

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1 Author(s)
Roine, T. ; Dept. of Inf., Oslo Univ.

A method for building fast, optimized bundled data circuits from a specialized CMOS standard cell library is presented. The method has been successfully used for the design of a FIFO buffer for a multicomputer network. This chip, which contains about 19000 transistors in a 1.5 μm CMOS process, achieves a throughput of about 150 million symbols per second

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on

Date of Conference:

3-5 Nov 1994