Referenced Items are not available for this document.
We propose a quantitative measure for evaluating the timing-reliability of asynchronous circuits designed on a variety of delay model. Using the measure, we evaluate the timing-reliability, as well as the speed performance and hardware cost, for various building blocks of asynchronous systems. Finally, we give a guideline for choosing valid delay models for the design of dependable asynchronous processors
Published in:
Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on
Date of Conference: 3-5 Nov 1994
- Page(s):
- 22 - 31
- Meeting Date :
- 03 Nov 1994-05 Nov 1994
- Print ISBN:
- 0-8186-6210-7
- INSPEC Accession Number:
- 4973547
- Conference Location :
- Salt Lake City, UT
- Digital Object Identifier :
- 10.1109/ASYNC.1994.656283
- Product Type:
- Conference Publications
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