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Tools for validating asynchronous digital circuits

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5 Author(s)
Ashkinazy, Aaron ; Genashor Corp., Belle Mead, NJ, USA ; Edwards, D. ; Farnsworth, C. ; Gendel, G.
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Asynchronous design methodologies can yield designs that are smaller and/or consume less power, than their synchronous counterparts. Traditional tools, oriented toward synchronous designs, may miss critical asynchronous design problems. This paper describes the modeling methodology and hazard analysis of the SlMIC logic simulator that address asynchronous designs. It also describes tools and a methodology for generating accurate timing models from SPICE simulations and for analyzing and viewing dynamic power consumption. Finally, it presents a case study illustrating the use of these tools in a leading-edge asynchronous design

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on

Date of Conference:

3-5 Nov 1994