By Topic

Optimized implementations of the multi-configuration DFT technique for analog circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Renovell ; Lab. d'Inf. Robotique Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France ; F. Azais ; Y. Bertrand

The paper describes an approach to optimize the application of the multi-configuration DFT technique for analog circuits. This technique allows to emulate the circuit in a number of new test configurations targeting the maximum fault coverage. The brute force application of the multi-configuration is shown to produce a very significant improvement of the original poor testability. An optimized approach is proposed to apply this DFT technique in a more refined way. The optimization problem consists in choosing among the various permitted test configurations, a set that leads to the best testability/cost trade-off. This set is selected according to ordered requirements: (i) the fundamental requirement of maintaining the maximum fault coverage and (ii) non-fundamental requirements of satisfying some user-defined cost functions such as test time, silicon overhead or performance degradation. Results are given that exhibit very interesting features in terms of either test procedure simplicity or DFT penalty reduction

Published in:

Design, Automation and Test in Europe, 1998., Proceedings

Date of Conference:

23-26 Feb 1998