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Coding Last Level STT-RAM Cache For High Endurance And Low Power

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4 Author(s)
Yazdanshenas, S. ; Iran University of Science and Technology, Tehran ; Ranjbar Pirbast, M. ; Fazeli, M. ; Patooghy, A.

STT-RAM technology has recently emerged as one of the most promising memory technologies. However, its major problems, limited write endurance and high write energy, are still preventing it from being used as a drop-in replacement of SRAM cache. In this paper, we propose a novel coding scheme for STT-RAM last level cache based on the concept of value locality. We reduce switching probability in cache by swapping common patterns with limited weight codes (LWC) to make writes less often as well as more uniform. We also define some policies for swapping these patterns. Our evaluation shows that bit write variance in memory cells can be reduced by about 20% on average resulting in a more uniform wear-out directly enhancing lifetime and improving cell reliability. In addition, writes in cache lines can be reduced by about 12% compared to one of the most effective circuit level techniques known as early write termination (EWT) [12]. Our method increases memory hierarchy access time by about 0.08% on average, which is negligible. We have shown that our method doesnt adversely affect last level cache energy-delay2. The non-uniformity caused by the coding scheme can be used for another coding scheme at main memory or L1 cache depending on their technologies.

Published in:

Computer Architecture Letters  (Volume:PP ,  Issue: 99 )