Referenced Items are not available for this document.
A bi-thread pipeline RISC microcontroller working together with a simple but efficient arithmetic coprocessor is proposed as digital signal processor. The structure has a Dual Architecture in which the main thread is used to manage the interfacing process and to run the algorithm and the slave thread is used only to control the “hard” computation in the arithmetic coprocessor that performs the sum of products. For coprocessor we have a sequential machine with a good mean working time. The paper presents the machine architecture and the associated organisation
Published in:
Semiconductor Conference, 1997. CAS '97 Proceedings., 1997 International
(Volume:2
)
Date of Conference: 7-11 Oct 1997
- Page(s):
- 585 - 588 vol.2
- Meeting Date :
- 07 Oct 1997-11 Oct 1997
- Print ISBN:
- 0-7803-3804-9
- INSPEC Accession Number:
- 5900399
- Conference Location :
- Sinaia
- Digital Object Identifier :
- 10.1109/SMICND.1997.651329
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