Skip to Main Content
This chapter analyzes the main nonideal mechanisms affecting the performance of both switched-capacitor (SC) and continuous-time (CT) ?>?> modulators implemented in CMOS process. The first part of the chapter is devoted to circuit errors with large influence on the behavior of SC-?>?>Ms, such as integrator leakage, capacitor mismatch, settling errors, and kT/C noise. The second part of the chapter covers the dominant circuit errors in CT-?>?>Ms, especially clock jitter, excess loop delay, and time-constant errors. The main sources of distortion in both types of ?>?>Ms are also discussed. System-level considerations, behavioral models, and closed-form expressions are obtained for the influence of each nonideality. From them, estimable guidelines for the design of ?>?>Ms can be extracted. These are put into practice in a case study at the end of the chapter.