Skip to Main Content
CMP (Chip Multiprocessor) based architectures have offered a promising solution in tomorrow's high performance computing demands. Topology and routing policy are playing key roles in designing such architectures to develop a NoC (Network-on-Chip). Major influencing design metrics include scalability, modularity, transport latency, parallelism, and, efficient load-balancing (to avoid generation of hot spots). Efficiency of topology as well as good routing policy is again counted in terms of its ability of fault tolerance and its deadlock prevention scheme. In this work, our primary objective was to design an efficient scalable NoC architecture with efficient fault tolerant routing policies to improve performance of a NoC from all these aspects. This not only reduces the network latency considerably but also tries to balance the load of the network as well as ensures that the packet will always reach the destination through the possible shortest deadlock free path.