By Topic

FL2STAR: A novel topology for on-chip routing in NoC with fault tolerance and deadlock prevention

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ghosal, P. ; Bengal Eng. & Sci. Univ., Howrah, India ; Das, T.S.

CMP (Chip Multiprocessor) based architectures have offered a promising solution in tomorrow's high performance computing demands. Topology and routing policy are playing key roles in designing such architectures to develop a NoC (Network-on-Chip). Major influencing design metrics include scalability, modularity, transport latency, parallelism, and, efficient load-balancing (to avoid generation of hot spots). Efficiency of topology as well as good routing policy is again counted in terms of its ability of fault tolerance and its deadlock prevention scheme. In this work, our primary objective was to design an efficient scalable NoC architecture with efficient fault tolerant routing policies to improve performance of a NoC from all these aspects. This not only reduces the network latency considerably but also tries to balance the load of the network as well as ensures that the packet will always reach the destination through the possible shortest deadlock free path.

Published in:

Electronics, Computing and Communication Technologies (CONECCT), 2013 IEEE International Conference on

Date of Conference:

17-19 Jan. 2013