By Topic

Die-to-die and within-die fabrication variation of 65nm CMOS technology PMOS transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)

Study and understanding of transistor and circuit variations caused by the fabrication process has become an important factor for integrated circuits as the device dimensions become smaller. Effects on clock frequency and IC performance caused by die-to-die and within-die variations have made it important to incorporate process variations in circuit simulators to correctly model the working of the present IC technology. This paper demonstrates the microscopic parameter variation modeling of die-to-die and within-die variations for 65nm CMOS fabrication technology by using the HiSIM surface-potential-based compact model. It is found that for accurate variation modeling of Vth and Ion from die-to-die and within-die primary consideration of only four parameters, namely substrate doping (NSUBC), pocket-implantation doping (NSUBP), carrier mobility degradation due to gate-interface roughness (MUESR1) and channel length change (XLD) is sufficient. In addition to these, modeling of within-die variation requires inclusion of a small variation for a fifth parameter describing the depletion charge contribution for the effective-electric field (NDEP). Variation analysis is done for wide p-MOSFETs (W=10μm) as a function of gate length.

Published in:

Electronics, Computing and Communication Technologies (CONECCT), 2013 IEEE International Conference on

Date of Conference:

17-19 Jan. 2013