By Topic

20-Bit RISC and DSP System Design in an FPGA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Amit Kumar Singh Tomar ; Lakshmi Narain Coll. of Technol., India ; Rita Jain

These days, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer (RISC) core, and many operations - such as discrete cosine transform (DCT), inverse DCT, discrete Fourier transform (DFT), and fast Fourier transform (FFT)--are performed by a digital signal processor (DSP) system. Here, the authors present the design of a RISC and DSP system that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.

Published in:

Computing in Science & Engineering  (Volume:16 ,  Issue: 2 )