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Testability preserving and enhancing transformations for robust delay fault testability

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3 Author(s)
A. Karkare ; Dept. of Comput. Sci. & Eng., IIT, Kanpur, India ; M. Singla ; A. Jain

Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET)

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998