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A low power floating point accumulator

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3 Author(s)
R. V. K. Pillai ; Concordia Univ., Montreal, Que., Canada ; D. Al-Khalili ; A. J. Al-Khalili

In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998