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A Historical Review of Low-Power, Low-Voltage Digital MOS Circuits Development

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1 Author(s)
Kiyoo Itoh ; Hitachi Ltd., Tokyo, 203-00, Japan

The development of low-power (LP), low-voltage (LV) (or LPLV) digital MOS circuits, fueled by a strong need for highend microcomputers (MPUs) and explosive growth in portable systems, has surely contributed to the current boom in MOS large-scale integration (LSI). This article reviews such digital MOS circuits as they have been developed over the last 50 years, since the advent of integrated circuits (ICs). A particular emphasis is placed on MPUs, systems-on-a-chip (SoCs), and SRAMs and DRAMs; the discussion is based mainly on papers presented at the International Solid-State Circuits Conference (ISSCC) and the Symposium on VLSI Circuits. Flash memories that necessitate unique circuits for high density rather than low power and high speed are excluded.

Published in:

IEEE Solid-State Circuits Magazine  (Volume:5 ,  Issue: 1 )