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A 27–34 GHz CMOS medium power amplifier with a flat power performance

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4 Author(s)
Chao-Hsiuan Tsay ; Dept. of Electrical Engineering and Graduate Institute of Communication Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei, 10617 Taiwan ; Jui-Chih Kao ; Kun-Yao Kao ; Kun-You Lin

This paper presents a 27-34 GHz medium power amplifier in 65-nm CMOS technology. The amplifier is designed to amplify the LO signals from the 30-GHz VCO in a 60-GHz sub-harmonic direct-conversion system. The proposed amplifier achieves a measured gain of higher than 22.8 dB from 27 to 34 GHz, and the gain deviation is within 1 dB. The measured results show a PAE up to 13% at 1-dB compression power (P1dB), and a 7.7-dBm P1dB at 30 GHz. The peak PAE and the saturation power (Psat) are 23.3% and 10.6 dBm at 30 GHz, respectively. The P1dB is between 6.8 and 7.7 dBm while the Psat is between 9.7 and 10.8 dBm from 27 to 34 GHz. The chip size is 0.36 mm2 including all testing pads.

Published in:

2012 Asia Pacific Microwave Conference Proceedings

Date of Conference:

4-7 Dec. 2012