By Topic

The last barrier: on-chip antennas

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Cheema, H.M. ; Electr. Eng. Dept., King Abdullah Univ. of Sci. & Tech. (KAUST), Thuwal, Saudi Arabia ; Shamim, A.

This paper has presented a comprehensive overview of on-chip antennas, which remain the last bottleneck for achieving true SoC RF solutions. CMOS remains the mainstream IC technology choice but is not well suited for on-chip antennas, requiring the use of innovative design techniques to overcome its shortcomings. Codesign of circuits and antennas provide leverage to the designer to achieve optimum performance. The layout of on-chip antennas is dictated by foundry specific rules whereas characterization of on-chip antennas requires special text fixtures. For future highly integrated SoC solutions, foundries will have to provide special layers for efficient on-chip antenna implementations, as they currently do for on-chip inductors. In many of the emerging applications such as THz communication, implantable systems and energy harvesting, on-chip antennas have shown immense potential and are likely to play a major role in shaping up future communication systems.

Published in:

Microwave Magazine, IEEE  (Volume:14 ,  Issue: 1 )