Referenced Items are not available for this document.
The demand for higher data rates in serial links has exacerbated the problem of power consumption, motivating extensive work on receiver and transmitter building blocks. This paper presents a half-rate clock and data recovery circuit and a deserializer that employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz jitter frequency.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:48
,
Issue:
3
)
Date of Publication: March 2013
- Page(s):
- 684 - 697
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 13324210
- Digital Object Identifier :
- 10.1109/JSSC.2013.2237692
- Product Type:
- Journals & Magazines
- Date of Publication :
- 22 January 2013
- Date of Current Version :
- 20 February 2013
- Issue Date :
- March 2013
- Sponsored by :
- IEEE Solid-State Circuits Society
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