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The demand for higher data rates in serial links has exacerbated the problem of power consumption, motivating extensive work on receiver and transmitter building blocks. This paper presents a half-rate clock and data recovery circuit and a deserializer that employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz jitter frequency.
Date of Publication: March 2013