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A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

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10 Author(s)
Lee, Y.-H. ; Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan ; Peng, S.-Y. ; Chiu, C.-C. ; Wu, A.C.-H.
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A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 ${rm mm}^{2}$ in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 ${rm V}/mu{rm s}$ as well as the improved MIPS performance by 5.6 times was achieved.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 4 )