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A column-parallel SA ADC with linearity calibration for CMOS imagers

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6 Author(s)
Shan-Ju Tsai ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Yen-Chun Chen ; Chih-Cheng Hsieh ; Wen-Hsu Chang
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This paper presents a 10-bit column-parallel successive approximation analog-to-digital converter (SA-ADC) with linearity calibration for CMOS imager. A multiple segmented charge redistribution capacitive digital-to-analog converter (MS-C-DAC) is utilized to reduce the DAC array size. A new linearity calibration method with adaptive reset configuration (ARC) of DAC is also proposed to solve the inherent mismatch issue of segmented DAC. The calibration technique ARC effectively eliminates three types of DAC error, i.e. (1) inaccurate serial capacitances, (2) parasitic capacitance on the charge conservation nodes, (3) mismatch of MSB capacitance. A prototype chip has been fabricated and verified in 0.18um CMOS technology. The new calibration method improves DNL from +5.62/-0.48 LSB to +0.33/-0.4 LSB, INL from +3.44/-4.93 LSB to +0.07/-1.81 LSB and SNDR from 46.63dB to 51.27dB at 240kS/s sampling rate. The whole chip consumes 35.46uW at a single 1.8V supply operation.

Published in:

Sensors, 2012 IEEE

Date of Conference:

28-31 Oct. 2012