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Device Scaling Considerations for Nanophotonic CMOS Global Interconnects

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3 Author(s)
Manipatruni, S. ; Components Res., Intel Corp., Hillsboro, OR, USA ; Lipson, M. ; Young, I.A.

We introduce an analytical framework to understand the path for scaling nanophotonic interconnects to meet the energy and footprint requirements of CMOS global interconnects. We derive the device requirements for sub-100 fJ/cm/bit interconnects including tuning power, serialization-deserialization energy, and optical insertion losses. Using CMOS with integrated nanophotonics as an example platform, we derive the energy/bit, linear, and areal bandwidth density of optical interconnects. We also derive the targets for device performance which indicate the need for continued improvements in insertion losses (<;8 dB), laser efficiency, operational speeds (>40 Gb/s), tuning power (<;100 μW/nm), serialization-deserialization (<;10 fJ/bit/Operation), and necessity for spectrally selective devices with wavelength multiplexing (>6 channels).

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Selected Topics in Quantum Electronics, IEEE Journal of  (Volume:19 ,  Issue: 2 )