Referenced Items are not available for this document.
Programming for CUDA devices presents the paradigm of warp-synchronous nature. This paper covers an implementation of an AES decryption kernel that makes use of warp-synchronicity. The operation of the various types of memories found in a CUDA device also required some analysis for a warp-synchronous implementation. The CUDA based implementation of AES256 was tested on several CUDA devices of various compute capabilities against the original single-threaded CPU implementation on various machines using encrypted messages of sizes ranging from 2MiB to 1GiB. The time taken for the GPUs to decrypt a message has varied between GPU architectures, with some achieving a 6x speedup.
Published in:
Performance Computing and Communications Conference (IPCCC), 2012 IEEE 31st International
Date of Conference: 1-3 Dec. 2012
- Page(s):
- 203 - 204
- ISSN :
- 1097-2641
- Print ISBN:
- 978-1-4673-4881-2
- INSPEC Accession Number:
- 13228049
- Conference Location :
- Austin, TX
- Digital Object Identifier :
- 10.1109/PCCC.2012.6407714
- Product Type:
- Conference Publications
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