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AES decryption using warp-synchronous programming

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2 Author(s)
Quirem, S. ; Dept. of Electr. & Comput. Eng., Univ. of Texas at San Antonio, San Antonio, TX, USA ; Byeong Kil Lee

Programming for CUDA devices presents the paradigm of warp-synchronous nature. This paper covers an implementation of an AES decryption kernel that makes use of warp-synchronicity. The operation of the various types of memories found in a CUDA device also required some analysis for a warp-synchronous implementation. The CUDA based implementation of AES256 was tested on several CUDA devices of various compute capabilities against the original single-threaded CPU implementation on various machines using encrypted messages of sizes ranging from 2MiB to 1GiB. The time taken for the GPUs to decrypt a message has varied between GPU architectures, with some achieving a 6x speedup.

Published in:

Performance Computing and Communications Conference (IPCCC), 2012 IEEE 31st International

Date of Conference:

1-3 Dec. 2012