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Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that often limit performance improvement and power reduction. However, stacking active layers of silicon will lead to increased power density and overall higher temperatures in a 3D chip implementation for many designs. Thermal sensors are therefore crucial for run-time thermal management of 3DICs. A thermal sensor distribution method customized for 3DICs is introduced in this paper. A new 3D thermal map modeling which facilitates efficient and very fast analyses is embodied in this thermal sensor distribution algorithm. The 3D thermal map modeling is based on scaled hotspot areas, depending on the distance of a stacked layer from the heatsink and also thermal effects of the layers on each other. Our results indicate that for a 4-layer stacked 3DIC, consisting of two layers of quad-core processors and one layer of L2 cache and one layer of main memory, less than 4.4% in maximum sensors reading error can be accomplished with a 53x speedup in the thermal evaluation time and thermal sensor distribution algorithm implementation. Furthermore, the number of needed sensors is 44% lower than that of conventional 2D thermal sensor distribution methods.