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This paper presents a frequency-translating bandpass ΔΣ modulator that uses single-path mixing within the ΔΣ feedback loop to downconvert a 4-MHz signal band from IF1 = 225 MHz at the input to IF2 = 25 MHz at the output. The proposed ΔΣ modulator is designed with a sixth-order continuous-time loop filter and a 3-bit quantizer. The quantizer operates at a sampling frequency of 100 MHz, which is lower than IF1 and, therefore, reduces both the power consumption and the sensitivity to timing errors relative to a conventional bandpass ΔΣ modulator. Furthermore, the loop filter implements noise shaping primarily at IF 2, which reduces the sensitivity to coefficient variations. The prototype chip was fabricated in 65-nm CMOS with an active area of 0.55 mm2. It achieves an SNDR of 55 dB over a 4-MHz signal bandwidth, and consumes 13 mW from a 1-V power supply.