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This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent ΔΣ time-to-digital converter (TDC) and an infinite impulse response (IIR)-based noise cancellation scheme. The proposed subexponent ΔΣ TDC generates adaptively scaled exponent-only information to track the finest resolution that prevents overloading for a given input environment. In addition, IIR-based noise cancellation provides easy filtering of delta-sigma modulator noise without tightened matching constraints. The DPLL fabricated in 0.13- μm CMOS consumes 8.6 mW and shows the subexponent operation and IIR noise cancellation. The measured phase noise of DPLL is - 98 dBc/Hz at 200-kHz offset and -111 dBc/Hz at 3-MHz offset with 500-kHz loop bandwidth.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:59 , Issue: 11 )
Date of Publication: Nov. 2012