Referenced Items are not available for this document.
Eight-transistor (8T) dual-port static random access memory (DP-SRAM) suffers from read and write disturbances at low voltages when both ports are accessed simultaneously, and write disturbance dominates the VDDmin in high-speed applications. This brief proposes a write-assist 8T (WA8T) cell to suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power consumption. We fabricated a 1-Mbit DP-SRAM with WA8T testchip using a 40-nm CMOS process. The proposed WA8T device achieved a 120-mV improvement in VDDmin with less than 1% area overhead.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on
(Volume:59
,
Issue:
11
)
Date of Publication: Nov. 2012
- Page(s):
- 790 - 794
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 13196229
- Digital Object Identifier :
- 10.1109/TCSII.2012.2228398
- Product Type:
- Journals & Magazines
- Date of Publication :
- 19 December 2012
- Date of Current Version :
- 04 January 2013
- Issue Date :
- Nov. 2012
- Sponsored by :
- IEEE Circuits and Systems Society
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