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It is easy to adjust the parameters for field-solver inductance extraction models to fit a single measurement. However, more effort is required to calibrate a model for a representative collection of line widths, layers, and fabrication runs. Numerically calculated inductance is also a strong function of segment size. A segment size is selected to optimize extraction accuracy versus speed for large RSFQ logic cells. InductEx is then calibrated for this segment size. Measured data from 54 test structures of different widths and layers, repeated on many chips over 22 wafers of Hypres's 4.5 kA/cm2 mask aligner process and 48 test structures from 5 wafers for the wafer stepper process, were used to find the Hypres process averages. Artificial changes to InductEx layer parameters such as mask-wafer bias and penetration depth are used to first reduce skew between results for different widths, and then differences between layers. This results in a set of calibrated process parameters for inductance calculations with InductEx for both the mask aligner and wafer stepper processes from Hypres. Calibrated inductance calculation results agree with the average measurements with a root-mean-square error smaller than 2.3% over the full range of line widths from 0.8 μm to 20 μm, showing InductEx as a useful tool for narrow-line inductance calculations.
Date of Publication: June 2013