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This letter describes a very simple implementation of a digital pulse width modulator (DPWM) under 100 ps resolution in low-cost field-programmable gate arrays (FPGAs). The implementation is based on internal carry chains and logic resources which are present in most FPGA families. The proposed approach does not require manual routing or placement, consumes few hardware resources, and does not rely heavily on specialized phase-locked loop or clock management resources. A 50-MHz switching frequency DPWM with 60-ps resolution and a 1-MHz switching frequency DPWM with 90-ps resolution are experimentally demonstrated, with monotonicity and excellent linearity.
Date of Publication: Oct. 2013